View UPD77210F1-DA2_306600.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
PD77210, 77213
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
The PD77210 and 77213 are 16-bit fixed-point digital signal processors (DSP). Compared with the existing members of the PD77111 Family, the PD77210 Family consumes less power and is ideal for battery-driven mobile terminal applications such as PDAs and cellular telephones. The P77210 Family is DSP is also compatible with the PD77111 Family at the binary level. The PD77210 Family consists of the PD77210 and 77213. Unless otherwise specified, the PD77210 Family refers to the entire family. If there are some differences in function or operation among family products, they are described under their respective names. The functions of the PD77210 Family are described in detail in the following user's manuals. Refer to these manuals when designing your system.
PD77210 Family User's Manual - Architecture: PD77016 Family User's Manual - Instructions:
In preparation U13116E
FEATURES
* Instruction cycle (operating clock):
PD77210 PD77213
* Memory
6.25 ns MIN. (160 MHz MAX.) 8.33 ns MIN. (120 MHz MAX.)
-Internal instruction memory:
PD77210 :RAM 31.5 Kwords x 32 bits PD77213 :RAM 15.5 Kwords x 32 bits
ROM 64 Kwords x 32 bits -Data memory:
PD77210 :RAM 30 Kwords x 16 bits x 2 planes (X and Y data memories)
External memory space 1 Mwords x 16 bits (common to X and Y data memories)
PD77213 :RAM 18 Kwords x 16 bits x 2 planes (X and Y data memories)
ROM 32 Kwords x 16 bits x 2 planes (X and Y data memories) External memory space 1 Mwords x 16 bits (common to X and Y data memories) * Peripheral -Audio serial interface: 1 channel -Time-division serial interface: 1 channel -16-bit host interface: 1 channel -16-bit general-purpose port -16-bit timer: 2 channels -Peripheral-memory DMA transfer function -SD (Secure Digital) card interface :PD77213 only
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U15203EJ3V0DS00 (3rd edition) Date Published November 2001 NS CP(K) Printed in Japan
The mark
shows major revised points.
(c)
2001
PD77210, 77213
* Supply voltage -DSP core supply voltage: -I/O pin supply voltage: 1.425 to 1.65 V (MAX. operating speed 120 MHz), 1.55 to 1.65 V (MAX. operating speed 160 MHz) PD77210 only 2.7 to 3.6 V
ORDERING INFORMATION
Parts Number Package 161-pin plastic fine pitch BGA (10 x 10) 144-pin plastic LQFP (fine pitch) (20 x 20) 161-pin plastic fine pitch BGA (10 x 10) 144-pin plastic LQFP (fine pitch) (20 x 20)
PD77210F1-DA2 PD77210GJ-8EN PD77213F1-xxx-DA2 PD77213GJ-xxx-8EN
Remark xxx indicates ROM code suffix.
2
Data Sheet U15203EJ3V0DS
BLOCK DIAGRAM
Peripheral unit X bus External memory External memory I/O
Y bus SD Card I/O
Note
Serial I/O (AUDIO)
Peripheral-memory transfer bus
X memory
Y memory
R0 to R7
Serial I/O (TDM)
Data Sheet U15203EJ3V0DS
Host I/O
Peripheral bus
X memory data addressing unit
Y memory data addressing unit Data memory unit MAC 16 x 16 + 40 40 ALU (40) BSFT
DMA controller
Interrupt controller
Main bus
Operation unit
Program control unit Port
PD77210, 77213
Interrupt control Timer
Loop control stack
PC stack
Instruction memory
CPU control IE I/O RESET CSTOP HALTS STOPS
Clock control
Note PD77213 only
CLKOUT CLKIN PLL
3
PD77210, 77213
FUNCTIONAL PIN BLOCK
+1.5 V +3.3 V
Serial interface (time division serial)
TSO TSORQ TSOEN TSCK TSI TSIEN TSIAK
IVDD
EVDD RESET INTmn
16
Reset and interrupt
CLKIN CLKOUT PLL0 to PLL3 STOPS CSTOP HALTS
Clock
4
Serial interface (audio serial)
ASOEN/LRCLK ASIEN/MCLK ASCK/BCLK ASI ASO SDDAT0 SDCR SDCLK SDMON P0 to P15 HCS HA0, HA1 HRD HRE HWR HWE HD0 to HD15
System control
SD card interface
Note
Port
16
MA0 to MA19 MD0 to MD15 MRD MWR MHOLDRQ MHOLDAK MBSTB MWAIT TIMOUT TDO, TICE TCK, TDI, TMS, TRST GND
20 16
External data memory interface
2
Host interface
Timer
16
2 4
For debugging
Note PD77213 only Caution Some port pins, host interface pins, serial interface pins, interrupt pins, and SD card interface pins are alternate function pins. Remark m, n = 0 to 3
4
Data Sheet U15203EJ3V0DS
DSP FUNCTION LIST
Item Memory space (words x bits) Int. instruction RAM Int. instruction ROM Data RAM (X/Y memory) Data ROM (X/Y memory) Ext. instruction memory Ext. data memory (X/Y memory) Data Sheet U15203EJ3V0DS Instruction cycle (at maximum operating speed) Multiple 15.3 ns (65 MHz) Integer multiple of x1 to 8 (external pin) Peripheral Serial interface 2 channels (speech CODEC) Host interface General-purpose port (I/O programmable) 8-bit bus 4 bits 8 bits 13.3 ns (75 MHz) Integer multiple of x1 to 16 (mask option) Integer multiple of x1 to 16 (external pin) 1 channel (audio CODEC) 16-bit bus 16 bits (some are alternative with host) 2 channels (time-division, audio) 6.25 ns (160 MHz) 32 K x 16 each None 16 K x 16 each None None 8 K x 16 each None 1 M x 16 1 M x 16 (8 K x 16, using SD I/F) 8.33 ns (120 MHz) None 16 K x 16 each 32 K x 16 each None 32 K x 16 each
PD77110
35.5 K x 32 None 24 K x 16 each
PD77111
1 K x 32
PD77112
PD77113A
3.5 K x 32 48 K x 32
PD77114
PD77115
11.5 K x 32 None 16 K x 16 each
PD77210
31.5 K x 32
PD77213
15.5 K x 32 64K x 32
31.75 K x 32 3 K x 16 each
16 K x 16 each
30 K x 16 each
18 K x 16 each
Integer multiple of x10 to 64 (external pin)
PD77210, 77213
Timer
None
1 channel (16-bit resolution)
2 channels (16-bit resolution) - SD card I/F DSP core: 1.5 V I/O pins: 3.3 V
Others Supply voltage
-
-
- DSP core: 2.5 V I/O pins: 3 V
-
-
SD card I/F
Package
100-pin TQFP
80-pin TQFP 80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin TQFP 80-pin FBGA
161-pin FBGA 144-pin LQFP
5
PD77210, 77213
PIN CONFIGURATIONS
161-pin plastic fine pitch BGA (10 x 10) *PD77210F1-DA2 *PD77213F1-xxx-DA2
(Bottom View) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P N M L K J H G F E D C B A A B C D E F G H J K L M N P (Top View)
Index mark
6
Data Sheet U15203EJ3V0DS
PD77210, 77213
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 NC NC
Pin Name
Pin No. C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E11 E12 E13 E14 F1 F2 F3 F4 F11 F12 F13 F14 G1 G2 G3 G4 G11 G12 G13 G14 H1
Pin Name EVDD P10/HD10/INT22 P11/HD11/INT32 P12/HD12/INT03 GND GND P1/INT10 GND GND GND GND TMS TICE MD12 MD15 P14/HD14/INT23 P15/HD15/INT33 P13/HD13/INT13 GND NC GND MD14 MD9 MD11 EVDD HD1 HD2 HD0 MD10 MD13 MD7 EVDD HD3 HD5 HD4 GND GND MD8 MD2 MD6 IVDD
Pin No. H2 H3 H4 H11 H12 H13 H14 J1 J2 J3 J4 J11 J12 J13 J14 K1 K2 K3 K4 K11 K12 K13 K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4
Pin Name HD7 HD6 GND MD5 MD4 MD1 MD3 EVDD HCS HA1 HWR GND MD0 MBSTB IVDD HA0 HRD TIMOUT ASO GND MWR MWAIT EVDD HWE HRE GND GND TSIEN GND GND MA8 GND MA14/SDDAT0Note GND MHOLDRQ MRD MHOLDAK EVDD ASCK/BCLK ASOEN/LRCLK TSOEN
Pin No. M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
Pin Name TSORQ MA0 MA4 MA5 MA10 MA12 MA15/ReservedNote MA19/SDCLKNote MA18/SDCRNote EVDD NC NC ASIEN/MCLK TSCK TSIAK MA1 MA2 MA7 MA9 MA11 MA16/ReservedNote MA17/ReservedNote NC NC NC NC ASI TSO TSI EVDD IVDD MA3 MA6 EVDD MA13/SDMONNote EVDD NC NC
P5/INT11 P2/INT20 GND EVDD IVDD IVDD PLL0 STOPS EVDD TRST NC NC NC NC P7/INT31 P6/INT21 P3/INT30 CLKOUT IVDD PLL3 PLL1 CSTOP I.C. TCK NC NC EVDD P8/HD8/INT02 P9/HD9/INT12 P4/INT01 P0/INT00 CLKIN PLL2 HALTS RESET I.C. TDI TDO GND
Note MA13 to MA19 pins of the PD77213 are alternate function pins.
Data Sheet U15203EJ3V0DS
7
PD77210, 77213
144-pin plastic LQFP (fine pitch) (20 x 20) (Top View) *PD77210GJ-8EN *PD77213GJ-xxx-8EN
MHOLDRQ MA19/SDCLKNote MA18/SDCRNote
MWR MRD MHOLDAK
MD15 MD14 MD13 MD12 MD11 MD10 GND EVDD MD9 MD8 MD7 MD6
MD1 MD0 MBSTB MWAIT
GND TCK TDI TMS TRST I.C. I.C. EVDD GND RESET STOPS CSTOP HALTS PLL0 PLL1 PLL2 PLL3 IVDD GND CLKIN IVDD GND IVDD GND CLKOUT EVDD GND P0/INT00 P1/INT10 P2/INT20 P3/INT30 P4/INT01 P5/INT11 P6/INT21 P7/INT31 GND
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 1 108 2 107 3 106 4 105 5 104 6 103 7 102 8 101 9 100 10 99 11 98 12 97 13 96 14 95 15 94 16 93 17 92 18 91 19 90 20 89 21 88 22 87 23 86 24 85 25 84 26 83 27 82 28 81 29 80 30 79 31 78 32 77 33 76 34 75 35 74 36 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
EVDD GND
EVDD
GND TICE TDO
MD3 MD2 GND IVDD
GND EVDD
MD5 MD4
EVDD Note MA17/Reserved Note MA16/Reserved Note MA15/Reserved Note MA14/SDDAT0 Note MA13/SDMON MA12 MA11 MA10 GND EVDD MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 GND IVDD GND EVDD MA1 MA0 TSIAK TSORQ TSI TSIEN TSCK TSO TSOEN ASI ASIEN/MCLK ASCK/BCLK GND
P15/HD15/INT33 EVDD
EVDD
EVDD GND HCS
P9/HD9/INT12 P10/HD10/INT22
P11/HD11/INT32 P12/HD12/INT03
P13/HD13/INT13 P14/HD14/INT23
Note MA13 to MA19 pins of the PD77213 are alternate function pins.
8
Data Sheet U15203EJ3V0DS
HRE HWR HWE TIMOUT ASOEN/LRCLK ASO EVDD GND
GND P8/HD8/INT02
GND HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7
IVDD GND
HA0 HA1 HRD
PD77210, 77213
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND TCK TDI TMS
Pin Name
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 EVDD GND
Pin Name
Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Pin Name GND ASCK/BCLK ASIEN/MCLK ASI TSOEN TSO TSCK TSIEN TSI TSORQ TSIAK MA0 MA1 EVDD GND IVDD GND MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 EVDD GND MA10 MA11 MA12 MA13/SDMON
Note
Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Pin Name GND EVDD MA18/SDCRNote MA19/SDCLKNote MHOLDRQ MHOLDAK MRD MWR MWAIT MBSTB MD0 MD1 EVDD GND IVDD GND MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 EVDD GND MD10 MD11 MD12 MD13 MD14 MD15 TDO TICE GND EVDD
P8/HD8/INT02 P9/HD9/INT12 P10/HD10/INT22 P11/HD11/INT32 P12/HD12/INT03 P13/HD13/INT13 P14/HD14/INT23 P15/HD15/INT33 EVDD GND HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 IVDD GND EVDD GND HCS HA0 HA1 HRD HRE HWR HWE TIMOUT ASOEN/LRCLK ASO EVDD GND
TRST I.C. I.C. EVDD GND RESET STOPS CSTOP HALTS PLL0 PLL1 PLL2 PLL3 IVDD GND CLKIN IVDD GND IVDD GND CLKOUT EVDD GND P0/INT00 P1/INT10 P2/INT20 P3/INT30 P4/INT01 P5/INT11 P6/INT21 P7/INT31 GND
MA14/SDDAT0
Note
MA15/ReservedNote MA16/Reserved
Note
MA17/Reserved EVDD
Note
Note MA13 to MA19 pins of the PD77213 are alternate function pins.
Data Sheet U15203EJ3V0DS
9
PD77210, 77213
Pin Name
ASCK ASI ASIEN ASO ASOEN BCLK CLKIN CLKOUT CSTOP EVDD GND HALTS HD0 to HD15 HCS HA0, HA1 HRD HRE HWE HWR I.C. IVDD INTmn LRCLK MBSTB MCLK MHOLDAK MHOLDRQ MRD MWR :Audio Serial Clock Input/Output :Audio Serial Data Input :Audio Serial Input Enable :Audio Serial Data Output :Audio Serial Output Enable :Bit Clock Input/Output :Clock Input :Clock Output :Clear Stop Mode :Power Supply for I/O Pins :Ground :Halt Status Signal Output :Host Data Bus :Host Chip Select :Host Data Access :Host Read :Host Read Enable :Host Write Enable :Host Write :Internal Connection :Power Supply for DSP Core :Interrupt (m,n=0 to 3) :Left Right Clock Input/Output :External Data Memory Bus Strobe :Master Clock Input :External Data Memory Bus Hold Acknowledge :External Data Memory Bus Hold Request :External Data Memory Read Output :External Data Memory Write Output TSORQ TSOEN TSIEN TSO TSI TSIAK SDDAT0 SDMON STOPS TCK TDI TDO TICE TIMOUT TMS TRST TSCK NC P0 to P15 PLL0-PLL3 Reserved RESET SDCLK SDCR MWAIT :External Data Memory Access Wait Input :Non-Connection :Port :PLL Multiple Rate Set :Reserved :Reset :SD Card Clock Output :SD Card Command Output/Response Input :SD Card Data Input/Output :SD Card Access Monitor :Stop Status Signal Output :Test Clock Input :Test Data Input :Test Data Output :Test In-Circuit Emulator :Timer Time Out Monitor Output :Test Mode Select :Test Reset :Time Division Multiplex Serial Clock Input :Time Division Multiplex Serial Data Input :Time Division Multiplex Serial Input Acknowledge :Time Division Multiplex Serial Input Enable :Time Division Multiplex Serial Data Output :Time Division Multiplex Serial Output Enable :Time Division Multiplex Serial Output Request
MA0 to MA19 :External Data Memory Address Bus
MD0 to MD15 :External Data Memory Bus
10
Data Sheet U15203EJ3V0DS
PD77210, 77213
CONTENTS
1. PIN FUNCTIONS....................................................................................................................................13
1.1 Description of Pin Functions ........................................................................................................................13 1.2 Connection of Unused Pins ..........................................................................................................................21 1.2.1 Connection of functional pins ..................................................................................................................21 1.2.2 Connection of non-functional pin .............................................................................................................22
2. FUNCTIONAL OUTLINE .......................................................................................................................23
2.1 Program Control Unit.....................................................................................................................................23 2.1.1 CPU control .............................................................................................................................................23 2.1.2 Interrupt control .......................................................................................................................................23 2.1.3 Loop control stack ...................................................................................................................................23 2.1.4 PC stack ..................................................................................................................................................23 2.1.5 Clock control............................................................................................................................................23 2.1.6 Instruction memory ..................................................................................................................................24 2.2 Operation Unit ................................................................................................................................................24 2.2.1 General-purpose registers (R0 to R7) .....................................................................................................24 2.2.2 Multiply accumulator (MAC) ....................................................................................................................24 2.2.3 Arithmetic logic unit (ALU) .......................................................................................................................24 2.2.4 Barrel shifter (BSFT)................................................................................................................................24 2.3 Data Memory Unit...........................................................................................................................................24 2.3.1 Data memory ...........................................................................................................................................24 2.3.2 Data addressing unit................................................................................................................................25 2.4 Peripheral Unit................................................................................................................................................25 2.4.1 Serial interface (SIO) ...............................................................................................................................25 2.4.2 Host interface (HIO).................................................................................................................................25 2.4.3 General-purpose I/O port (PIO) ...............................................................................................................26 2.4.4 External memory interface (MIO).............................................................................................................26 2.4.5 Timers (TIM1 and TIM2) ..........................................................................................................................26 2.4.6 Interrupt controller (INTC)........................................................................................................................26 2.4.7 DMA controller (PMT) ..............................................................................................................................26 2.4.8 SD card interface (SDCIF).......................................................................................................................26 2.4.9 Debug interface (IEIO).............................................................................................................................26
3. CLOCK GENERATOR...........................................................................................................................27 4. RESET FUNCTION ................................................................................................................................28
4.1 Hardware Reset ..............................................................................................................................................28
5. FUNCTION OF BOOT-UP ROM...........................................................................................................28
5.1 Boot at Reset ..................................................................................................................................................28 5.1.1 Memory boot............................................................................................................................................28 5.1.2 Host boot .................................................................................................................................................29 5.1.3 Serial boot ...............................................................................................................................................29 5.2 Reboot.............................................................................................................................................................29 5.2.1 Memory reboot ........................................................................................................................................29
Data Sheet U15203EJ3V0DS
11
PD77210, 77213
5.2.2 Host reboot ............................................................................................................................................. 30 5.2.3 Serial reboot ........................................................................................................................................... 30
6. STANDBY MODE.................................................................................................................................. 31
6.1 Halt Mode ....................................................................................................................................................... 31 6.2 Stop Mode ...................................................................................................................................................... 31
7. MEMORY MAP...................................................................................................................................... 32
7.1 Instruction Memory ....................................................................................................................................... 32 7.1.1 Instruction memory map ......................................................................................................................... 32 7.1.2 Interrupt vector table............................................................................................................................... 33 7.2 Data Memory .................................................................................................................................................. 34 7.2.1 Data memory map .................................................................................................................................. 34 7.2.2 Internal peripherals ................................................................................................................................. 35
8. GENERAL-PURPOSE PORT AND INTERRUPT ............................................................................... 38
8.1 General-purpose Port Pins ........................................................................................................................... 38 8.2 Interrupt Pin ................................................................................................................................................... 38
9. INSTRUCTION ....................................................................................................................................... 39
9.1 Outline of Instruction .................................................................................................................................... 39 9.2 Instruction Set and Its Operation................................................................................................................. 40
10. ELECTRICAL SPECIFICATIONS....................................................................................................... 46 11. PACKAGE DRAWINGS...................................................................................................................... 69 12. RECOMMENDED SOLDERING CONDITIONS................................................................................. 71
12
Data Sheet U15203EJ3V0DS
PD77210, 77213
1. PIN FUNCTIONS
Because the pin numbers differ depending on the package, see the column for the package to be used in the tables below. 1.1 Description of Pin Functions * Power supply pins
Pin Name Pin No. 144-pin LQFP IVDD 18,21,23,57, 88,123 EVDD 8,26,37,47,59, 71,86,98,108, 110,121,133, 144 161-pin FBGA A7,A8,B7,H1, J14, P7 A6,A11,C1, C14,F1,F14, J1,K14,M1, M14,P6,P10, P12 GND 1,9,19,22,24, 27,36,38,48, 58,60,72,73, 87,89,99,109, 122,124,134, 143 A5,C13,D4,D5, D7,D8,D9,D10, E4,E11,G4, G11,H4,J11, K11,L3,L4,L6, L7,L9,L11 - Ground These are ground pins. - - - Power supply for DSP core (+1.5 V) These pins supply power to the DSP core. Power supply for I/O (+3.3 V) These pins supply power to the external interface pins. - I/O Function Alternate Pin -
Remark Please supply voltage to the IVDD and EVDD pins simultaneously.
Data Sheet U15203EJ3V0DS
13
PD77210, 77213
* Clock and system control pins
Pin Name Pin No. 144-pin LQFP CLKIN 20 161-pin FBGA C6 Input Clock input This pin inputs a clock to operate the PD77210 Family. CLKOUT 25 B6 Output Internal system clock output This pin outputs the internal system clock that is the clock input from CLKIN and which is multiplied by the PLL circuit. PLL0 to PLL3 14 to 17 A9,B9,C7,B8 Input PLL multiple setting input These pins set a clock multiple of the PLL circuit. * PLL3: PLL2: PLL1: PLL0 0000: x10 0011: x16 0110: x22 1001: x28 1100: x40 1111: x64 HALTS 13 C8 Output HALT mode status output This pin is asserted active in halt mode and stop mode. STOPS 11 A10 Output Stop mode status output This pin is asserted active in stop mode. CSTOP 12 B10 Input Stop mode clear signal input Stop mode is cleared when this pin is asserted active. - - - 0001: x12 0100: x18 0111: x24 1010: x30 1101: x48 0010: x14 0101: x20 1000: x26 1011: x32 1110: x56 - - I/O Function Alternate Pin -
14
Data Sheet U15203EJ3V0DS
PD77210, 77213
* Reset and interrupt pins
Pin Name Pin No. 144-pin LQFP RESET 10 161-pin FBGA C9 Input Internal system reset signal input This pin initializes the PD77210 Family. INT00 INT01 INT02 INT03 INT10 INT11 INT12 INT13 INT20 INT21 INT22 INT23 INT30 INT31 INT32 INT33 28 32 39 43 29 33 40 44 30 34 41 45 31 35 42 46 C5 C4 C2 D3 D6 A3 C3 E3 A4 B4 D1 E1 B5 B3 D2 E2 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Maskable external interrupt input These pins input external interrupts. P0 P4 P8/HD8 P12/HD12 P1 P5 P9/HD9 P13/HD13 P2 P6 P10/HD10 P14/HD14 P3 P7 P11/HD11 P15/HD15 I/O Function Alternate Pin -
Data Sheet U15203EJ3V0DS
15
PD77210, 77213
* External data memory interface
Pin Name Pin No. 144-pin LQFP MA0 to MA19Note 84, 85, 90 to 97, 100 to 107, 111, 112 161-pin FBGA M6,N6,N7,P8, M7,M8,P9,N8, L8,N9,M9,N10, M10,P11,L10, M11,N11,N12, M13,M12 MD0 to MD15 119,120, 125 to 132, 135 to 140 J12,H13,G13, H14,H12,H11, G14,F13,G12, E13,F11,E14, D13,F12,E12, D14 MWR 116 K12 Output (3S) Write output This pin outputs a write strobe signal for the external data memory. MRD 115 L13 Output (3S) Read output This pin outputs a read strobe signal for the external data memory. MHOLDAK 114 L14 Output Hold acknowledge signal This pin goes low when the external device is granted use of the external data memory bus of the - - - I/O (3S) 16-bit data bus These pins input/output data when the external data memory is accessed. - Output (3S) Address bus of external data memory These pins output an address when the external data memory is accessed. I/O Function Alternate Pin SDCLK, SDCR, SDDAT0, SDMON
PD77210 Family.
MHOLDRQ 113 L12 Input Hold request signal The external device inputs a low level to this pin when it uses the external data memory bus of the -
PD77210 Family.
MWAIT 117 K13 Input Wait signal input This pin inserts wait cycles when the PD77210 Family accesses the external data memory. * 0: Inserts wait cycles. * 1: Does not insert wait cycles. MBSTB 118 J13 Output Bus strobe signal This pin goes low while the PD77210 Family uses the external data memory bus. - -
Note MA13 to MA19 pins of the PD77213 are alternate function pins. Remark Those pins marked "3S" in the above table enter the high-impedance state under the following conditions: MA0 to MA19, MRD, and MWR: When the bus is released (MHOLDAK = low level) MD0 to MD15: When the external data memory is not accessed and when the bus is released (MHOLDAK = low level)
16
Data Sheet U15203EJ3V0DS
PD77210, 77213
* Timer
Pin Name Pin No. 144-pin LQFP TIMOUT 68 161-pin FBGA K3 Output Time out monitor This pin is asserted active when the timer times out. I/O Function Alternate Pin -
* Serial interface
Pin Name Pin No. 144-pin LQFP ASCK/ BCLK 74 161-pin FBGA M2 I/O Audio serial clock input/output ASCK:Audio serial clock input BCLK:Serial clock I/O ASO 70 K4 Output (3S) ASI ASOEN/ LRCLK 76 69 P3 M3 Input I/O Audio serial data input Audio serial output enable/left right clock input output ASOEN:Audio serial output enable input LRCLK:Left right clock I/O ASIEN/ MCLK 75 N3 Input Audio serial input enable/master clock input output ASIEN:Audio serial input enable input MCLK:Master clock input (in master mode) TSCK TSO 79 78 N4 P4 Input Output (3S) TSI TSORQ TSOEN TSIEN TSIAK 81 82 77 80 83 P5 M5 M4 L5 N5 Input Output Input Input Output Time-division serial data input Time-division serial output request Time-division serial output enable Time-division serial input enable Time-division serial input acknowledge - - - - - Clock input for time division serial Time-division serial data output - - - - - Audio serial data output - I/O Function Alternate Pin -
Remark Those pins marked "3S" in the above table enter the high-impedance state when data transmission is completed and when the hardware reset (RESET) signal is input.
Data Sheet U15203EJ3V0DS
17
PD77210, 77213
* Host interface
Pin Name Pin No. 144-pin LQFP HA1 63 161-pin FBGA J3 Input Host address 1 This pin specifies a register that is accessed by the host interface pins (HD7 to HD0, or HD15 to HD0). * 1: The host interface status register (HST) is accessed. * 0: The host transmit data register (HDT (out)) is accessed for read (HRD = 0) and the host receive data register (HDT (in)) is accessed for write (HWR = 0). HA0 62 K1 Input Host address 0 This pin specifies a register that is accessed by HD7 to HD0 in 8-bit mode. This pin is invalid in 16-bit mode. * 1: Bits 15 to 8 of HST, HDT (in), and HDT (out) are accessed. * 0: Bits 7 to 0 of HST, HDT (in), and HDT (out) are accessed. HCS HRD HWR HRE HWE HD0 to HD7 61 64 66 65 67 49 to 56 J2 K2 J4 L2 L1 F4,F2,F3,G1, G3,G2,H3,H2 Input Input Input Output Output I/O (3S) Chip select input Host read input Host write input Host read enable output Host write enable output 8-bit host data bus These pins constitute a host data bus in 8-bit host mode. Access to 16-bit data for input/output is controlled by the HA0 pin, and the data is accessed two times such that it is divided into two blocks of 8bit data. In 16-bit mode, the lower 8 bits of the data are input/output. HD8 to HD15 39 to 46 C2,C3,D1,D2, D3,E3,E1,E2 I/O (3S) Host data bus These pins constitute a host data bus in 16-bit host mode. They input/output 16-bit data with HD0 to HD7. P8 to P15/ INT02, INT12, INT22, INT32, INT03, INT13, INT23, INT33 - - - - - - - I/O Function Alternate Pin -
Remark Those pins marked "3S" in the above table enter the high-impedance state while the host interface is not being accessed.
18
Data Sheet U15203EJ3V0DS
PD77210, 77213
* I/O port
Pin Name Pin No. 144-pin LQFP P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 28 29 30 31 32 33 34 35 39 40 41 42 43 44 45 46 161-pin FBGA C5 D6 A4 B5 C4 A3 B4 B3 C2 C3 D1 D2 D3 E3 E1 E2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General-purpose I/O port I/O Function Alternate Pin INT00 INT10 INT20 INT30 INT01 INT11 INT21 INT31 INT02/HD8 INT12/HD9 INT22/HD10 INT32/HD11 INT03/HD12 INT13/HD13 INT23/HD14 INT33/HD15
* Debugging interface
Pin Name Pin No. 144-pin LQFP TDO 141 161-pin FBGA C12 Output (3S) TICE TCK TDI TMS TRST 142 2 3 4 5 D12 B12 C11 D11 A12 Output Input Input Input Input For debugging This interface pins are used when a debugger is used. - - - - - I/O Function Alternate Pin -
Remark Those pins marked "3S" in the above table enter the high-impedance state while the debugging interface is not being accessed.
Data Sheet U15203EJ3V0DS
19
PD77210, 77213
*SD card interface (PD77213 only)
Pin Name Pin No. 144-pin LQFP SDCLK 112 161-pin FBGA M12 Output SD card clock output * Leave this pin open. SDCR 111 M13 I/O (3S) SD cord command/response Input: Response Output: Command * Leave pull-up. SDDAT0 104 L10 I/O (3S) SD card data input/output Input: Read data Output: Write data * Leave pull-up. SDMON 103 P11 Output SD card interface access monitor This pin outputs a high level when the SD card interface is being accessed. 1: SD card interface being accessed 0: SD card interface not being accessed Reserved 105 to 107 M11, N11, N12 - Reserved for future function expansion. This pin becomes high impedance when the SD card interface is being used. MA15 to MA17 MA13 MA14 MA18 I/O Function Alternate Pin MA19
Remark Those pins marked "3S" in the above table enter the high-impedance state when the SD card interface is not being accessed. * Others
Pin Name Pin No. 144-pin LQFP I.C. 6, 7 - 161-pin FBGA B11, C10 - - Internally connected. Leave these pins open. NC A1,A2,A13, A14,B1,B2, B13,B14,E5, N1,N2,N13, N14,P1,P2, P13,P14 No connection. Leave these pins open. - I/O Function Alternate Pin -
Caution If any signal is input to these pins or if these pins are read, the correct operation of the PD77210 Family is not guaranteed.
20
Data Sheet U15203EJ3V0DS
PD77210, 77213
1.2 Connection of Unused Pins 1.2.1 Connection of functional pins Connect the unused pins as shown in the table below.
Pin Name STOPS, HALTS CSTOP CLKOUT P0 to P15 HD0 to HD7 HA0, HA1 HCS, HRD, HWR HRE, HWE TIMOUT ASCK, TSCK ASI, TSI ASIEN, TSIEN ASOEN, TSOEN, LRCLK ASO, TSO TSORQ TSIAK MA0 to MA19 MD0 to MD15 MRD, MWR MHOLDRQ MBSTB, MHOLDAK MWAIT TCK TDO, TICE TMS, TDI TRST
Note 2 Note 1
I/O Output Input Output I/O I/O Input Input Output Output Input Input Input Input Leave open.
Recommended Connection
Connect to GND via a pull-down resistor. Leave open. Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor. Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor. Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor. Connect to EVDD via a pull-up resistor. Leave open. Leave open. Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor.
Connect to GND via a pull-down resistor.
Output Output Output Output I/O Output Input Output Input Input Output Input Input
Leave open.
Leave open. Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor. Leave open. Connect to EVDD via a pull-up resistor. Leave open. Connect to EVDD via a pull-up resistor. Connect to GND via a pull-down resistor. Leave open. Leave open (this pin is internally pulled up). Leave open (this pin is internally pulled down).
Notes 1. These pins may left opened if the HCS, HRD,and HWR are fixed to the high level. However, connect these pins as recommended in the HALT and STOP modes when the power consumption must be lowered. 2. These pins may leave opened if the external data memory is not accessed in the program. However, connect these pins as recommended in the HALT and STOP modes when the power consumption must be lowered. Caution Unused alternate-function pins should be handled in accordance with the processing specified for the pin function of the initial setting.
Data Sheet U15203EJ3V0DS
21
PD77210, 77213
1.2.2 Connection of non-functional pin
Pin name I.C. NC I/O - - Leave open. Leave open. Recommended Connection
22
Data Sheet U15203EJ3V0DS
PD77210, 77213
2. FUNCTIONAL OUTLINE
2.1 Program Control Unit This unit controls the execution of PD77210 Family by executing instructions and controlling branching, loop, interrupts, clock, and standby mode. 2.1.1 CPU control A three-stage pipeline architecture is employed so that all instructions, except branch instructions and some others, can be executed with one system clock. 2.1.2 Interrupt control The interrupt control circuit services the interrupt requests input to the interrupt controller by an external pin (INTmn) or internal peripherals (such as the serial interface, host interface, timer, and DMA controller). The interrupt of each interrupt source can be individually enabled or disabled. In addition, multiple interrupts are also supported. 2.1.3 Loop control stack A loop function without any hardware overhead is realized. A 4-level loop stack is provided to support multiple loops. 2.1.4 PC stack A 15-level PC stack that stacks the program counter supports multiple interrupts/subroutine calls. 2.1.5 Clock control A PLL and a divider are internally provided as a clock generator so that an externally input clock is multiplied or divided and supplied as the operating clock to the PD77210 Family. The multiple of the PLL can be set by using external pins (PLL0 to PLL3) within a range of x10 to 64. The division ratio can be set by using a register in a range of /1 to 16. The clock control register (CLKC) controls the power (ON/OFF) to the PLL, selects a clock source, controls the output divider, and controls the output of the CLKOUT pin. Two types of standby modes are available so that the power consumption can be reduced when the PD77210 Family is standing by. *HALT mode: Current consumption falls to several mA upon execution of the HALT instruction. This mode is released by an interrupt or hardware reset. *STOP mode: Current consumption falls to hundreds of A
Note
upon execution of the STOP instruction.
This mode is released by hardware reset or inputting a signal to CSTOP pin. Note When the PLL is stopped
Data Sheet U15203EJ3V0DS
23
PD77210, 77213
2.1.6 Instruction memory Of the instruction RAM, 64 words are allocated as interrupt vectors. The PD77210 is provided with an instruction RAM of 31.5 Kwords. The PD77213 is provided with an instruction RAM of 15.5 Kwords and instruction ROM of 64 Kwords. A boot-up ROM that boots up the instruction RAM is also provided, and the instruction RAM can be initialized or rewritten by means of a memory boot (booting from an internal or external data space), host boot (booting via a host interface), or serial boot (booting via a serial interface). 2.2 Operation Unit This unit performs multiplication, addition, logic, and shift operations, and consists of a 40-bit multiply accumulator, a 40-bit data ALU, a 40-bit barrel shifter, and eight 40-bit general-purpose registers. 2.2.1 General-purpose registers (R0 to R7) These eight 40-bit registers input/output operands and load/store data to/from data memory. Each register consists of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to 16), and R0E to R7E (bits 39 to 32). Depending on the type of the operation, RnL, RnH, and RnE are used either as one register or in combination. 2.2.2 Multiply accumulator (MAC) The multiply accumulator performs multiplication of two 16-bit data items and addition or subtraction between the result of the multiplication and one 40-bit data item, and then outputs 40-bit data. A shifter (MSFT: MAC shifter) is provided at the preceding stage of the MAC, so that the 40-bit data that is to be added to or subtracted from the multiplication result can be arithmetically shifted 1 bit or 16 bits to the right before addition or subtraction. 2.2.3 Arithmetic logic unit (ALU) The ALU accepts one or two 40-bit data items as input, performs an arithmetic or logical operation, and then outputs 40-bit data. 2.2.4 Barrel shifter (BSFT) The BFST accepts 40-bit data items as input, shifts the data to the left or right by an arbitrary number of bits, and then outputs 40-bit data. The data can be shifted to the right arithmetically, in which case the sign of the data is extended, or logically in which case 0 is inserted starting from the MSB. 2.3 Data Memory Unit The data memory unit consists of two planes of data memory spaces and two pairs of data addressing units. 2.3.1 Data memory Two data memory planes (X data memory and Y data memory) are provided. The data memory space includes a 64-word peripheral area. The PD77210 has a data RAM consisting of 30 Kwords x 2 planes. The PD77213 has a data RAM consisting of 18 Kwords x 2 planes, and has a data ROM consisting of 32 Kwords x 2 planes. In addition, They also have an external data memory interface that is used to connect an external 1 Mword data memory to the device.
24
Data Sheet U15203EJ3V0DS
PD77210, 77213
2.3.2 Data addressing unit An independent data addressing unit is provided for each of the X and Y data memory spaces. Each data addressing unit has four data pointers (DPn), four index registers (DNn), one module register (DMX or DMY), and an address ALU. 2.4 Peripheral Unit The peripheral unit has serial interfaces, a host interface, general-purpose I/O ports, timers, an external memory interface, and SD card interface (PD77213 only). All these internal peripherals are mapped to the X and Y data memory spaces and are accessed as memory-mapped I/Os by the program. 2.4.1 Serial interface (SIO) Two serial interface channels, an audio serial interface (ASIO) and a time-division serial interface (TDMSIO), are provided. The audio serial interface can be used in either of two modes: audio mode and standard mode. The standard mode is compatible with the existing PD77111 Family. The audio mode is compatible with the PD77115. The features of the audio mode are as follows: * Mode: Master mode and slave mode Master mode: Supports master clock input (MCLK), bit clock output (BCLK), LR clock output (LRCLK), 256 fs, 384 fs, and 512 fs. Slave mode: Bit clock input (BCLK) and LR clock input (LRCLK) * Frame format: 32- or 64-bit audio formats (LRCLK format) * Handshake: Handshaking with external devices by a dedicated frame signal (LRCLK) and with the internal circuitry by polling, wait, or interrupt The standard mode has the following features: *Serial clock: *Frame length: *Handshake: Supplied from an external source to each channel. The clock is shared for input and output by each channel. 8 or 16 bits, with MSB or LSB first selected for each channel. Handshaking with the external device by using a dedicated status signal and with the internal circuitry by polling, wait, or interrupt. The time-division serial interface divides the serial input/output signal into 1 to 32 time slots and allows several devices to share the serial bus. Because the T1 and E1 frame signals are considered. The time slot can be extended from 1 to 128. 2.4.2 Host interface (HIO) This is a parallel port that inputs/outputs data from/to an external host CPU and DMA controller. It can be used in either 8-bit parallel mode or 16-bit parallel mode. In the PD77210 Family, 16-bit registers are mapped to memory for input data, output data, and status. Handshaking with an external device is performed by using a dedicated status signal, and the internal circuitry handshaking is done by means of polling, wait, or interrupts. The 8-bit parallel mode is compatible with the existing members of the PD77111 Family. In 16-bit parallel mode, some port pins are used as host interface pins.
Data Sheet U15203EJ3V0DS
25
PD77210, 77213
2.4.3 General-purpose I/O port (PIO) This is a 16-bit I/O port that can be set to either input or output mode in 1-bit units. The external pins alternate between interrupt pins and host interface pins. By setting the mode of 8 bits of the port to host interface pin mode, the host interface can be set in the 16-bit parallel mode. 2.4.4 External memory interface (MIO) This interface accesses an external 1 Mwords data memory area in either of two modes: direct access and DMA access modes. In DMA access mode, access is made via a memory-mapped register. In direct access mode, the data paging register (DPR) is set to 0x3F and a page area is accessed as an access window. An address of the external memory consists of 20 bits with the 8-bit value of the index register added as bits 12 to 19. In DMA access mode, the address is automatically updated when a memory-mapped register is accessed. The address is updated in an increment addressing mode in which the address is simply incremented, or in twodimensional addressing mode in which an offset is added to each line length. The number of wait cycles to be inserted when the external memory is accessed can be specified by a register (MWAIT), within a range of 1 to 15. In addition, wait cycles can also be inserted by using the MWAIT pin. 2.4.5 Timers (TIM1 and TIM2) The PD77210 Family has two timer channels. These timers can be used as interval timers, event counters, watchdog timers, and free-run timers. The clock input to the timers is selected from the system clock, serial clock (ASCK or TSCK), external interrupt (INT00, INT10, INT20, or INT30), or output of each timer. The count value is 16 bits and the clock input by the prescaler can be divided by 1, 2, 4, 8, 16, 32, 64, or 128. 2.4.6 Interrupt controller (INTC) The interrupt controller has functions for selecting and masking interrupt signals. It controls the interrupt signal to be input to the DSP core. 2.4.7 DMA controller (PMT) The DMA controller realizes data transfer between the peripherals and memory (peripheral-memory transfer) in the background. It mitigates the software overhead generated by interrupt processing of the data input/output via SIO, HIO, MIO, and SDCIF (PD77213 only). Data of 14 Kwords at addresses 0x0000 to 0x37FF of the internal data RAM can be transferred by means of DMA. 2.4.8 SD card interface (SDCIF) The PD77213 supports SD Card interface. This interface is for access of SD card. It supports the DMA transfer for input data to internal data RAM. The SD card is accessed by using a dedicated routine of system ROM. 2.4.9 Debug interface (IEIO) The PD77210 Family has the following functions that conform to the JTAG (Joint Test Action Group) interface as a debug interface. A device conforming to JTAG has an access port dedicated to testing and can be tested independently of the internal logic. The PD77210 Family has registers and a control circuit for in-circuit emulation, in addition to the instruction registers, bypass registers, and boundary scan registers that are required by the JTAG Recommendation.
26
Data Sheet U15203EJ3V0DS
PD77210, 77213
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and supplies the clock to the PD77210 Family. The configuration of the clock generator is as illustrated below.
Standby mode Halt Stop
CLKIN
PLL controller
x m (m:10 to 64)
Output divider
Internal system clock
/ n (n:1 to 16)
CLKOUT
CLKC register
PLL0 to PLL3 Peripheral bus
The PLL is stopped immediately after reset. The clock input from the CLKIN pin is directly supplied to the
PD77210 Family internal circuitry and bootup commences. The PLL is started up in the boot routine and booting is
carried out via the PLL output clock (except in the case of non-boot or external memory boot). In the case of nonboot or external memory boot, when booting has finished, after the PLL is started up by setting the CLKC register from the user program, the clock source must be switched to the PLL, in which case the PLL must be locked. Note that 300 s are required between when the PLL is started up and when it is locked. The PLL multiplication rate is specified by the external pins PLL0 to PLL3. The PLL also has two lock range modes: 80 to 120 MHz and 120 to 160 MHz. The mode to be used is specified by the P3 pin during booting. The CLKC register is used to control turning on/off the PLL, select the clock source (external clock/multiplied clock/divided or non-divided output), control resetting the output divider, set the division ratio, and enable/disable CLKOUT pin output. When the output divider is selected, the high-level width of the clock output by the CLKOUT pin is equivalent to 1 cycle of the normal operation (which means that the clock does not have a duty factor of 50%). In halt mode, output of the divider circuit is automatically selected as the clock source. When the divider circuit is selected, the clock is not changed even if halt mode is set. In stop mode, the system clock supplied to the internal circuitry is masked. Because the PLL is not stopped automatically, it can recover from stop mode without PLL lock time. It is necessary to set the CLKC register by the program to stop the PLL.
Data Sheet U15203EJ3V0DS
27
PD77210, 77213
4. RESET FUNCTION
The device is initialized when a low level of the specified width is input to the RESET pin. 4.1 Hardware Reset The internal circuitry of the PD77210 Family is initialized when the RESET pin is asserted active (low level) for a specific period. When the RESET pin is then deasserted inactive (high level), booting of the instruction RAM is performed in accordance with the status of the port pins (P0, P1, P2, and P3), and then processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.
5. FUNCTION OF BOOT-UP ROM
The instruction RAM is booted up by using the internal boot-up ROM when power is applied or when the contents of the instruction memory are to be rewritten by the program. 5.1 Boot at Reset Immediately after release of a hardware reset, the boot program first reads general-purpose I/O port pins P0 to P3, and a boot mode (memory boot/host boot/serial boot) is determined by the bit patterns of these port pins. Once the booting processing has been completed, processing is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.
P2 0 0 0 0 1 1 1 P1 0 0 1 1 0 0 1 P0 0 1 0 1 0 1 0 Non-bootNote X memory initial boot Y memory initial boot XY memory initial boot External memory initial boot Host boot Serial boot Boot Mode
Note This setting is used when the PD77210 Family must be reset upon restoration from standby mode after a reset boot has been executed once.
P3 0 1 PLL lock range 120 to 160 MHz 80 to 120 MHz
5.1.1 Memory boot The instruction code stored in data memory is transferred to the instruction RAM. Depending on the data memory from which the instruction code is to be transferred, X memory boot (booting from the X data memory), Y memory boot (booting from the Y data memory), XY memory boot (booting from the X and Y data memories), or external memory boot (booting from the external data memory space) may be performed.
28
Data Sheet U15203EJ3V0DS
PD77210, 77213
5.1.2 Host boot The boot parameter and instruction code are obtained via the host interface and transferred to the instruction RAM. 5.1.3 Serial boot The boot parameter and instruction code are obtained via the serial interface and transferred to the instruction RAM. 5.2 Reboot The contents of the instruction RAM can be rewritten by calling the following reboot entries by the program.
Reboot Mode Entry Address Number Instruction Steps of Transfer Source Start Address Parameter Transfer Destination Transfer Destination Start Address Memory reboot X memory Y memory XY memories External memory Host reboot Serial reboot 0x1 0x2 0x3 0x4 0x5 0x6 R7L R7L R7L R7L R7L R7L DP3 DP7 DP3, DP7 DP3 - - R6L R6L R6L R6L R6L R6L DP2 DP6 DP2 DP2 DP2 DP2 Transfer Destination Page (DPR) R5L R5L R5L R5L R5L R5L
5.2.1 Memory reboot The instruction code stored into data memory is transferred to the instruction RAM. Depending on the data memory from which the instruction code is to be transferred, X memory reboot (rebooting from the X data memory), Y memory reboot (rebooting from the Y data memory), XY memory reboot (rebooting from the X and Y data memories), or external memory reboot (rebooting from the external data memory space) may be performed. Perform memory rebooting by setting the following parameters and calling the entry address by the corresponding rebooting method. * R7L: Number of instruction steps to be rebooted * DP3: First address of X memory storing instruction code (to reboot from X, XY or external memories) * DP7: First address of X memory storing instruction code (to reboot from Y or XY memories) * R6L: Transfer source data page register (DPR) (Specify 0x00 in the case of the internal data RAM area.) Index register (for external memory rebooting) * DP2: Transfer destination address of the instruction to be rebooted (to reboot from X, XY or external memories) * DP6: Transfer destination address of the instruction to be rebooted (to reboot from Y memories) * R5L: Transfer destination page register (DPR) (Specify 0x80 in the case of the internal instruction RAM area.)
Data Sheet U15203EJ3V0DS
29
PD77210, 77213
5.2.2 Host reboot The instruction code is obtained via the host interface and transferred to the instruction RAM. The entry address is 0x5. Host rebooting is executed by setting the following parameters and then calling this address. * R7L: Number of instruction steps to be rebooted * R6L: Host status register (HST) * DP2: Transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction RAM area) * R5L: Transfer destination data page register (DPR) (Specify 0x80 of the internal instruction RAM area.) 5.2.3 Serial reboot The instruction code is obtained via the serial interface (TDMSIO) and then transferred to the instruction RAM. The entry address is 0x6. Host rebooting is executed by setting the following parameters and then calling this address. * R7L: Number of instruction steps to be rebooted * R6L: Serial status register (SST) (Specify 0x0EC0.) * DP2: Transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction RAM area) * R5L: Transfer destination data page register (DPR) (Specify 0x80 of the internal instruction RAM area.)
30
Data Sheet U15203EJ3V0DS
PD77210, 77213
6. STANDBY MODE
The PD77210 Family can be set to either of two standby modes. Each mode can be set by executing the corresponding instruction. The power consumption can be reduced in these modes. 6.1 Halt Mode The halt mode can be set by executing the HALT instruction. In this mode, all the functions except the clock circuit and PLL are stopped and, therefore, the current consumption can be reduced. The device can be released from this mode by an interrupt or hardware reset. To release the device from halt mode by issuing an interrupt, the contents of the internal registers and memories are retained. It takes 10 to 20 system clocks to release the PD77210 Family from halt mode (if it is released by an interrupt). When releasing the device from halt mode by using hardware reset, the external clock must be selected as the clock source in advance that the contents of memories are retain. In halt mode, the clock circuit of the PD77210 Family supplies the clock divided by the ratio specified by the CLKC register as the internal system clock. The same applies to the clock output by the CLKOUT pin. 6.2 Stop Mode Stop mode is set when a STOP instruction is executed. In this mode, supply of the clock to the internal system is stopped. If the PLL is stopped before stop mode is set, all the functions, including the clock circuit and PLL, are stopped. As a result, only a leakage current flows and, therefore, the current consumption can be minimized. In this case, the external clock must be selected as the clock source in advance. The device is released from stop mode by a hardware reset or the CSTOP pin. To release the device from stop mode by using the CSTOP pin, the contents of the internal registers and memories are retained. When releasing the device from stop mode by using hardware reset, the external clock must be selected as the clock source in advance that the contents of memories are retain.
Data Sheet U15203EJ3V0DS
31
PD77210, 77213
7. MEMORY MAP
The PD77210 Family employs a Harvard architecture that separates the instruction memory space from the data memory space. 7.1 Instruction Memory 7.1.1 Instruction memory map The instruction memory space consists of 64 Kwords x 32 bits. The area at addresses 0x8000 to 0xFFFF is a paging area that supports a memory space of 64 Kwords or more by specifying a page by using the instruction paging register (IPR). The instruction ROM of the PD77213 exists in the paging area and is accessed as IPR=0x0 or 0x1. The paging area of the PD77210 is reserved for future expansion.
PD77210
0xFFFF 0xFFFF
PD77213
Paging area
Paging area (32 Kwords)
Paging area (32 Kwords)
Instruction ROM (32 Kwords)
Note
0x8000 0x7FFF
0x8000 0x7FFF
(IPR=0x0) (IPR=0x1) System area
Instruction RAM (31.5 Kwords)
0x4000 0x3FFF Instruction RAM (15.5 Kwords)
0x0200 0x01FF 0x0000
Boot-up ROM (512 words)
0x0200 0x01FF 0x0000
Boot-up ROM (512 words)
Note The higher 8 words of the instruction ROM (0xFFF8 to 0xFFFF) constitute system area. Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If these addresses are accessed, correct operation of accessed, correct operation of the device is not guaranteed. the device is not guaranteed. A paging area in which no IPR page exists cannot be accessed. If this kind of paging area is
32
Data Sheet U15203EJ3V0DS
PD77210, 77213
7.1.2 Interrupt vector table Addresses 0x200 to 0x23F of the instruction memory are assigned to entry points (vectors) of interrupts. Four instruction addresses are assigned to each interrupt source. Four interrupt sources are assigned to each interrupt vector. There are 12 vectors. By identifying the source in the vector, the PD77210 can use 38 interrupt sources and PD77213 can use 42 interrupt sources. Each of these interrupt sources can be masked by using the interrupt control register (ICR0 to ICR11).
Vector 0 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 Reset Reserved Reserved Reserved INT00 INT10 INT20 INT30 TSI input 1 Reserved Reserved Reserved Reserved INT01 INT11 INT21 INT31 TSIEN Interrupt Source 2 Reserved Reserved Reserved Reserved INT02 INT12 INT22 INT32 PMT ch0 (TSI input) 0x224 TSO output TSOEN PMT ch1 (TSO output) 0x228 ASI input ASIEN PMT ch2 (ASI input) 0x22C ASO output ASOEN PMT ch3 (ASO output) 0x230 HI input HWR PMT ch4 (HI input) 0x234 HO output HRD PMT ch5 (HO output) 0x238 TIMER ch0 TIMER ch1 PMT ch6 (MI input) 0x23C TIMER ch1 TIMER ch0 PMT ch7 (MO output) Reserved Reserved Reserved Reserved SDDAT inputNote (busy release) SDDAT outputNote SDCR output Note 3 Reserved Reserved Reserved Reserved INT03 INT13 INT23 INT33 SDCR input Note
Note
These interrupt sources are for the PD77213 only. When using the PD77210, they are reserved. 1. Reset is not an interrupt but is used as an entry of a vector. 2. It is recommended that the vector of an interrupt source that is not used branch to an abnormality processing routine.
Cautions
Data Sheet U15203EJ3V0DS
33
PD77210, 77213
7.2 Data Memory 7.2.1 Data memory map The data memory space consists of two planes: the X and Y memory spaces, each of which consists of 64 Kwords x 16 bits. The area of 0x8000 to 0xFFFF is a paging area that supports a memory space of 64 Kwords or more by specifying a page by using the data paging register (DPR). The DPR can be set in the same manner regardless of whether the X or Y memory space is accessed. Page 0x3F of DPR is a window to the external data memory. The Data ROM of the PD77213 exists in the paging area and is accessed as DPR=0x0. Page 0x80 of the DPR is shared by 0x0000 to 0x7FFF of the internal instruction RAM. The lower 16 bits of the 32-bit instruction RAM constitute the X data memory, while the higher 16 bits are the Y data memory. Because some pins of the PD77213 are shared with the SD card interface, the area that can be accessed when the SD card interface is being used is restricted. The address pins MA13 to MA19 are shared with the SD card interface. When the SD card interface is being used, therefore, only the 13-bit address area of MA0 to MA12 (8 Kwords) can be accessed.
PD77210
0xFFFF
Paging area 0xFFFF
PD77213
Paging area
Paging area (32 Kwords)
Note 1
External data memory window (32 Kwords)
Paging area (32 Kwords)
Data ROM (32 Kwords)
Note 2
External data memory window (32 Kwords)
0x8000 0x7FFF
(DPR=0x3F)
0x8000 0x7FFF System
(DPR=0x0)
(DPR=0x3F)
Data RAM (16 Kwords)
0x4000 0x3FFF 0x3800 0x37FF
0x5000 0x4FFF 0x4000 0x3FFF 0x3800 0x37FF
Data RAM (4 Kwords) Peripheral (2 Kwords)
Peripheral (2 Kwords)
Data RAM (14 Kwords)
0x0000 0x0000
Data RAM (14 Kwords)
Notes 1. If the paging register is set to a value other than 0x3F (external data memory window) or 0x80 (internal instruction RAM area), programs and data cannot be stored to the addresses of the paging area, nor can these addresses be accessed. 2. The higher 8 words of the data ROM (0xFFF8 to 0xFFFF) constitute system area. Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If these addresses are accessed, correct operation of accessed, correct operation of the device is not guaranteed. the device is not guaranteed. A paging area in which no DPR page exists cannot be accessed. If this kind of paging area is
34
Data Sheet U15203EJ3V0DS
PD77210, 77213
7.2.2 Internal peripherals The internal peripherals are mapped to the internal data memory space. Cautions 1. The register names shown in the above table are not reserved words in either assembler or C. To use these names in assembler or C, therefore, the user must define them. 2. The same register is accessed regardless of whether the X memory space or Y memory space is accessed, provided that the address is the same. 3. Different registers cannot be accessed simultaneously from the X and Y memory spaces. Memory-Mapped Peripherals (1/3)
X/Y Memory Address Register Name Function Peripheral Name 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 to 0x380F 0x3810 0x3811 0x3812 0x3813 to 0x381F 0x3820 0x3821 0x3822 to 0x383F 0x3840 0x3841 0x3842 0x3843 0x3844 0x3845 0x3846 0x3847 0x3848 0x3849 0x384A 0x384B 0x384C 0x384D to 0x384F 0x3850 0x3851 0x3852 0x3853 TSDT/SDT1 SST1 TSST TFMT TTXL TTXH TRXL TRXH Reserved area ASDT/SDT2 SST2 ASST Reserved area HDT HST Reserved area MDT MSHW MCST MWAIT MIDX MADRLI MADRHI MOFSI MLENI MADRLO MADRHO MOFSO MLENO Reserved area PMSA0 PMS0 PMC0 PMP0 TDM serial data register/Serial data register 1 Serial status register 1 TDM serial status register TDM frame format register TDM transfer slot register (low) TDM transfer slot register (high) TDM receive slot register (low) TDM receive slot register (high) Caution Do not access this area. Audio serial data register/Serial data register 2 Serial status register 2 Audio serial status register Caution Do not access this area. Host interface data register Host interface status register Caution Do not access this area. Memory data register Memory I/F setup/hold width setting register Memory I/F control/status register Memory I/F wait register Direct access index register Memory I/F input start address register (low) Memory I/F input start address register (high) Memory I/F input line offset register Memory I/F input line length register Memory I/F output start address register (low) Memory I/F output start address register (high) Memory I/F output line offset register Memory I/F output line length register Caution Do not access this area. PMT start address register 0 PMT size register 0 PMT control register 0 PMT address pointer 0 - PMT ch0 - MIO - HIO - ASIO(SIO2) TSIO(SIO1)
Data Sheet U15203EJ3V0DS
35
PD77210, 77213
Memory-Mapped Peripherals (2/3)
X/Y Memory Address Register Name Function Peripheral Name 0x3854 0x3855 0x3856 0x3857 0x3858 0x3859 0x385A 0x385B 0x385C 0x385D 0x385E 0x385F 0x3860 0x3861 0x3862 0x3863 0x3864 0x3865 0x3866 0x3867 0x3868 0x3869 0x386A 0x386B 0x386C 0x386D 0x386E 0x386F 0x3870 0x3871 0x3872 0x3873 0x3874 0x3875 0x3876 0x3877 0x3878, 0x3879 0x387A, 0x387B PMSA1 PMS1 PMC1 PMP1 PMSA2 PMS2 PMC2 PMP2 PMSA3 PMS3 PMC3 PMP3 PMSA4 PMS4 PMC4 PMP4 PMSA5 PMS5 PMC5 PMP5 PMSA6 PMS6 PMC6 PMP6 PMSA7 PMS7 PMC7 PMP7 PDT0 PCD0 PDT1 PCD1 PDT2 PCD2 PDT3 PCD3 Reserved area POWC PMT start address register 1 PMT size register 1 PMT control register 1 PMT address pointer 1 PMT start address register 2 PMT size register 2 PMT control register 2 PMT address pointer 2 PMT start address register 3 PMT size register 3 PMT control register 3 PMT address pointer 3 PMT start address register 4 PMT size register 4 PMT control register 4 PMT address pointer 4 PMT start address register 5 PMT size register 5 PMT control register 5 PMT address pointer 5 PMT start address register 6 PMT size register 6 PMT control register 6 PMT address pointer 6 PMT start address register 7 PMT size register 7 PMT control register 7 PMT address pointer 7 Port data register 0 Port command register 0 Port data register 1 Port command register 1 Port data register 2 Port command register 2 Port data register 3 Port command register 3 Caution Do not access this area. Power control register - Peripheral STOP mode PIO PMT ch7 PMT ch6 PMT ch5 PMT ch4 PMT ch3 PMT ch2 PMT ch1
36
Data Sheet U15203EJ3V0DS
PD77210, 77213
Memory-Mapped Peripherals (3/3)
X/Y Memory Address Register Name Function Peripheral Name 0x387C to 0x387F 0x3880 0x3881 0x3882 0x3883 0x3884 0x3885 0x3886 0x3887 0x3888 0x3889 0x388A 0x388B 0x388C to 0x388F 0x3890 0x3891 0x3892 0x3893 0x3894 0x3895 0x3896 0x3897 to 0x389F 0x38A0 0x38A1 0x38A2 0x38A3 0x38A4 0x38A5 0x38A6 0x38A7 0x38A8 0x38A9 to 0x38AF 0x38B0 0x38B1 to 0x38BF 0x38C0 0x38C1 0x38C2 to 0x38CF 0x38D0 0x38D1-0x3FFF Reserved area ICR0 ICR1 ICR2 ICR3 ICR4 ICR5 ICR6 ICR7 ICR8 ICR9 ICR10 ICR11 Reserved area TIR0 TCR0 TCSR0 Reserved area TIR1 TCR1 TCSR1 Reserved area CEFR CPR0 CAR0 CLIR0 CUIR0 CPR1 CAR1 CLIR1 CUIR1 Reserved area CLKC Reserved area IPR DPR Reserved area ADCR
Note
Caution Do not access this area. Interrupt control register 0 Interrupt control register 1 Interrupt control register 2 Interrupt control register 3 Interrupt control register 4 Interrupt control register 5 Interrupt control register 6 Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 Interrupt control register 11 Caution Do not access this area. Timer initial register 0 Timer count register 0 Timer control/status register 0 Caution Do not access this area. Timer initial register 1 Timer count register 1 Timer control/status register 1 Caution Do not access this area. Collect enable flag register Collect page register 0 Collect address register 0 Collect instruction data register (high) 0 Collect instruction data register (low) 0 Collect page register 1 Collect address register 1 Collect instruction data register (high) 1 Collection instruction data register (low) 1 Caution Do not access this area. Clock control register Caution Do not access this area. Instruction paging register Data paging register Caution Do not access this area. Additional I/F control register Caution Do not access this area.
- INTC
- TIM0
- TIM1
- IMC
- CLKC - Page register
- Additional IO -
Reserved area
Note PD77213 only. Do not access 0x38D0 of the PD77210.
Data Sheet U15203EJ3V0DS
37
PD77210, 77213
8. GENERAL-PURPOSE PORT AND INTERRUPT
8.1 General-purpose Port Pins The general-purpose port pins alternate with the interrupt or host interface pins. The configuration of the general-purpose port is illustrated below.
OE Port pin O I OE
Note
Port I/O
O Host I/O I Interrupt controller
Note P0 to P7 do not alternate with the host interfave pins.
8.2 Interrupt Pin The general-purpose port pin functions as an interrupt pin and the signal input to the port is always input to the interrupt controller. The interrupt controller recognizes the interrupt by detecting a falling edge. The output of the general-purpose port or host interface pin can be also used as an interrupt input. Pins HRD, HWR, ASOEN, ASIEN, TSOEN, and TSIEN are connected to the interrupt controller and can be used as interrupt pins.
38
Data Sheet U15203EJ3V0DS
PD77210, 77213
9. INSTRUCTION
9.1 Outline of Instruction One instruction consists of 32 bits. All the instructions, with some exceptions such as branch instructions, are executed with one system clock. The instruction cycle of the PD77210 is up to 6.25 ns. The instruction cycle of the
PD77213 is up to 8.33 ns. The following nine types of instructions are available.
(1) Trinomial instructions These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be specified. (2) Binomial instructions These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose registers can be specified. Some of these instructions allow one immediate value to be specified instead of a general-purpose register. (3) Monomial instructions These instructions specify an operation by the ALU. As the operand, a general-purpose register can be specified. (4) Load/store instructions These instructions specify 16-bit data transfer between memory and a general-purpose register. As the operand, any general-purpose register can be specified. (5) Register-to-register transfer instructions These instructions specify transfer between a general-purpose register and another register. (6) Immediate value setting instructions These instructions set an immediate value in the general-purpose registers and each register of the address operation unit. (7) Branch instructions These instructions specify branching of the program. (8) Hardware loop instructions These instructions specify the repetitive execution of an instruction. (9) Control instructions These instructions specify program control.
Data Sheet U15203EJ3V0DS
39
PD77210, 77213
9.2 Instruction Set and Its Operation Describe an operation in the operation field of each instruction in accordance with the description method of the operation representation format of the instruction. If two or more elements are available, select one of them. (a) Correspondence between representation format and selectable register The representation format and selectable register are as follows:
Representation Format ro, ro', ro" rl, rl' rh, rh' re reh dp dn dm dpx dpy dpx_mod dpy_mod dp_imm *xxx R0 to R7 R0L to R7L R0H to R7H R0E to R7E R0EH to R7EH DP0 to DP7 DN0 to DN7 DMX, DMY DP0 to DP3 DP4 to DP7 DPn, DPn++, DPn--, DPn##, DPn%%, !DPn## (n = 0 to 3) DPn, DPn++, DPn--, DPn##, DPn%%, !DPn## (n = 4 to 7) DPn## imm (n = 0 to 7) Contents of memory at address xxx (Example) If the contents of the DP0 register are 1000, *DP0 indicates the contents of memory address 1000. Selectable Register
40
Data Sheet U15203EJ3V0DS
PD77210, 77213
(b) Modifying data pointer The data pointer is modified only after memory access. The result of the modification becomes valid starting from the instruction that is executed immediately after. The data pointer cannot be modified without the memory access.
Example DPn DPn++ DPn-- DPn## Operation Nothing is executed (value of DPn is not changed). DPn DPn + 1 DPn DPn - 1 DPn DPn + DNn (Value of DN0 to DN7 corresponding to DP0 to DP7 is added.) Example: DP0 DP0 + DN0 DPn%% (n = 0 to 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH (n = 4 to 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH !DPn## Reverses bits of DPn and then accesses DPn. After memory access, DPn DPn + DNn DPn## imm DPn DPn + imm
(c) Instructions that can be described simultaneously Those instructions that can be described simultaneously are indicated by . (d) Status of overflow flag (OV) The status of the overflow flag is indicated by the following symbols: : No change
Caution If an overflow does not occur after an operation, the overflow flag is not reset and its status remains the same as before the operation.
: Set to 1 if an overflow occurs.
Data Sheet U15203EJ3V0DS
41
PD77210, 77213
Instruction Set
Flag Control Instruction Name Mnemonic Operation Instructions That Can Be Described Simultaneously
Immediate Value
Instruction Group
Load/Store
Monomial
Trinomial
Binomial
Transfer
Branch
Loop
Multiply add Multiply sub Trinomial operation Signed/unsigned multiply add Unsigned/unsigned multiply add
ro = ro + rh*rh' ro = ro - rh*rh' ro = ro + rh*rl (rl is in positive integer format.) ro = ro + rl*rl' (rl and rl' are in positive integer format.)
ro ro + rh*rh' ro ro - rh*rh' ro ro + rh*rl ro ro + rl*rl'

1-bit shift multiply add 16-bit shift multiply add Multiply Add Immediate add
ro = (ro >> 1) + rh*rh' ro = (ro >> 16) + rh*rh'
ro ro/2 + rh*rh' ro ro/2 + rh*rh' ro rh*rh' ro" ro + ro' ro' ro + imm (where imm 1) ro" ro - ro' ro' ro - imm (where imm 1) ro' ro >> rl ro' ro >> imm ro' ro >> rl ro' ro >> imm ro' ro << rl ro' ro << imm ro" ro & ro' ro' ro & imm ro" ro | ro' ro' ro | imm ro" ro^ro' ro' ro^imm

ro = rh*rh' ro" = ro + ro' ro' = ro + imm
Sub Immediate sub
ro" = ro - ro' ro' = ro - imm
Arithmetic right shift Immediate arithmetic right shift Binomial operation Logical right shift Immediate logical right shift Logical left shift Immediate logical left shift And Immediate and Or Immediate or Exclusive or Immediate exclusive or Less than
ro' = ro SRA rl ro' = ro SRA imm
ro' = ro SRL rl ro' = ro SRL imm
ro' = ro SLL rl ro' = ro SLL imm
ro" = ro & ro' ro' = ro & imm ro" = ro | ro' ro' = ro | imm ro" = ro^ro' ro` = ro^imm
ro" = LT (ro, ro')
if (ro < ro') {ro" 0x0000000001} else {ro" 0x0000000000}
42
Data Sheet U15203EJ3V0DS

OV
PD77210, 77213
Instruction Group
Described Simultaneously
Immediate Value
Load/Store
Monomial
Trinomial
Binomial
Transfer
Control
Branch
Loop
Clear Increment Decrement Absolute value
CLR (ro) ro' = ro + 1 ro' = ro - 1 ro' = ABS (ro)
ro 0x0000000000 ro' ro + 1 ro' ro - 1 if (ro < 0) {ro' -ro} else {ro' ro}

1's complement 2's complement Clip
ro' = ~ro ro' = -ro ro' = CLIP (ro)
ro' ~ro ro' -ro if (ro > 0x007FFFFFFF) {ro' 0x007FFFFFFF} elseif (ro < 0xFF80000000) {ro' 0xFF80000000} else {ro' ro}

Monomial operation
Round
ro' = ROUND (ro)
if (ro > 0x007FFF0000) {ro' 0x007FFF0000} elseif (ro < 0xFF80000000) {ro' 0xFF80000000} else {ro' (ro + 0x8000) & 0xFFFFFF0000} ro' log2 (1/ro) ro' ro ro' ro' + ro ro' ro' - ro if (sign (ro') = = sign (ro)) {ro' (ro' - ro) << 1} else {ro' (ro' + ro) << 1} if (sign (ro') = = 0) {ro' ro' + 1}
Exponent Substitution Accumulated add Accumulated sub Division
ro' = EXP (ro) ro' = ro ro' + = ro ro' - = ro ro' / = ro

Data Sheet U15203EJ3V0DS
43
OV
Flag
Instruction Name
Mnemonic
Operation
Instructions That Can Be
PD77210, 77213
Instruction Group
Described Simultaneously
Immediate Value
Load/Store
Monomial
Trinomial
Binomial
Transfer
Control
Branch
Loop
Parallel load/store
Notes 1, 2
ro = *dpx_mod ro' = *dpy_mod ro = *dpx_mod *dpy_mod = rh *dpx_mod = rh ro = *dpy_mod *dpx_mod = rh *dpy_mod = rh'
ro *dpx, ro' *dpy ro *dpx, *dpy rh *dpx rh, ro *dpy *dpx rh, *dpy rh' dest *dpx, dest' *dpy dest *dpx, *dpy source *dpx source, dest *dpy *dpx source, *dpy source' dest *addr *addr source dest *dp *dp source dest rl rl source rl mm dp imm dn imm dm imm
Partial load/store
Notes 1, 2, 3
dest = *dpx_mod dest' = *dpy_mod
Load/store
dest = *dpx_mod *dpy_mod = source *dpx_mod = source dest = *dpy_mod *dpx_mod = source *dpy_mod = source' Direct addressing load/store
Note 4
dest = *addr *addr = source dest = *dp_imm *dp_imm = source dest = rl rl = source rl = imm (where imm = 0 to 0xFFFF) dp = imm (where imm = 0 to 0xFFFF) dn = imm (where imm = 0 to 0xFFFF) dm = imm (where imm = 1 to 0xFFFF)
Immediate index load/store
Registerto-register transfer
Note 5
Register-to-register transfer
Note 6
Immediate value setting Immediate value setting
Notes 1. Of the two mnemonics, either or both can be described. 2. After transfer, modification specified by mod is performed. 3. dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl} 4. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = {0: X-0xFFFF: X (X memory), or 0: Y-0xFFFF: Y (Y memory)} 5. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl} 6. Select any of the registers (except the general-purpose registers) as dest and source.
44
Data Sheet U15203EJ3V0DS
OV
Flag
Instruction Name
Mnemonic
Operation
Instructions That Can Be
PD77210, 77213
Instruction Group
Described Simultaneously
Immediate Value
Load/Store
Monomial
Trinomial
Binomial
Transfer
Control
Branch
Loop
Jump Register-to-register jump Subroutine call
JMP imm JMP dp
PC imm PC dp SP SP + 1 STK PC + 1 PC imm
CALL imm
Branch
Register-to-register subroutine call
CALL dp
SP SP + 1 STK PC + 1 PC dp PC STK SP SP - 1 PC STK STK SP - 1 Restores interrupt enable flag. RC count RF 0 During repeat PC PC RC RC - 1 End PC PC + 1 RF 1 LC count LF 0 During loop PC PC + 1 (while PC < LEA) if (PC = LEA) PC LSA LC LC - 1 End PC PC + 1 LF 1
Return
RET
Interrupt return
RETI
Repeat
REP count
Start
Loop Hardware loop
LOOP count (Instruction of 2 lines or more)
Start
Loop pop
LPOP
LC LSR3 LE LSR2 LS LSR1 LSP LSP - 1 PC PC + 1 CPU stops. CPU stops, PLL, and OSC can be stopped by a user
No operation Halt Control Stop
NOP HALT STOP
Condition Forget interrupt
IF (ro cond) FINT
Condition judgment Discards interrupt request.
Data Sheet U15203EJ3V0DS
OV
Flag
Instruction Name
Mnemonic
Operation
Instructions That Can Be
45
PD77210, 77213
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25C)
Parameter Supply voltage Symbol IVDD EVDD Input voltage Output voltage Storage temperature Operating ambient temperature VI VO Tstg TA Condition For DSP core For I/O pins VI < EVDD + 0.5 V Rating - 0.5 to + 2.0 - 0.5 to + 4.6 - 0.5 to + 4.6 - 0.5 to + 4.6 - 65 to + 150 - 20 to + 70 Unit V V V V C C
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter Operating voltage Symbol IVDD Condition For DSP core (operating speed 120 MHz Max.) For DSP core (operating Note speed 160 MHz Max.) EVDD Input voltage VI For I/O pins MIN. 1.425 TYP. 1.50 MAX. 1.65 Unit V
1.55
1.60
1.65
V
2.7 0
3.3
3.6 EVDD
V V
Note
PD77210 only
Capacitance (TA = +25C, IVDD = 0 V, EVDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Condition f = 1 MHz, Pins other than those tested: 0 V MIN. TYP. 10 10 10 MAX. Unit pF pF pF
46
Data Sheet U15203EJ3V0DS
PD77210, 77213
DC Characteristics (Unless otherwise specified, TA = - 20 to + 70C, with IVDD and EVDD within recommended operating condition range)
Parameter High level input voltage Symbol VIHN VIHC VIHS Condition Pins other than below CLKIN RESET, P0 to P15, TSCK, TSIEN,TSOEN, ASCK, ASIEN, ASOEN Pins other than below CLKIN RESET, P0 to P15, TSCK, TSIEN,TSOEN, ASCK, ASIEN, ASOEN IOH = -100 A IOL = 2.0 mA VI = EVDD 0 -10 0 MIN. 0.7 EVDD 0.7 EVDD 0.8 EVDD TYP. MAX. EVDD EVDD EVDD Unit V V V
Low level input voltage
VILN VILC VILS
0 0 0
0.2 EVDD 0.2 EVDD 0.2 EVDD
V V V
High level output voltage Low level output voltage High level input leakage current Low level input leakage current High impedance leakage current Pull-up pin current Pull-down pin current Internal supply current [fclkin = 10 MHz, IVDD = 1.5 V, VIHN = VIHC = VIHS = EVDD, VIL = 0 V, no load, TA = 25C]
VOH VOL ILHN
0.8 EVDD 0.2 EVDD 10
V V
A A A A A
mA
ILLN
VI = 0 V 0 V VI EVDD TDI, TMS, 0 V VI EVDD TRST, 0 V VI EVDD During operating, fclk = 100 MHz, PLL multiple rate x10 In halt mode, fclk = 100 MHz, PLL multiple rate x 10, division rate 1/1 In stop modeNote 4, fclk = 0 Hz, PLL stop
0 -10 70 -70 35
Note 1
ILZ
IPUI IPDI IDD
20 -20
200 -200 70
Note 2
IDDH
20Note 3
mA
IDDS
PD77210 PD77213
240 120
A
Notes 1. The value is when MAC with Dual Load instruction 50% + nop instruction 50% are executed. It is roughly estimated at 0.35 mA/MHz. 2. The value is when a special program that brings about frequent switching inside the device is executed. It is roughly estimated at 0.7 mA/MHz. 3. The value is when the division rate is 1/1. It is roughly estimated at 0.2 mA/MHz + IDDS using the divided clock. 4. The value in stop mode is the value when PLL is stopped.
Data Sheet U15203EJ3V0DS
47
PD77210, 77213
Common Test Criteria of Switching Characteristics
RESET, P0 to P15, TSCK, TSIEN, TSOEN, ASCK, ASIEN, ASOEN
0.8 EVDD 0.5 EVDD 0.2 EVDD
Test Points
0.8 EVDD 0.5 EVDD 0.2 EVDD
Input (other than above)
0.7 EVDD 0.5 EVDD 0.2 EVDD
Test Points
0.7 EVDD 0.5 EVDD 0.2 EVDD
Output
0.5 EVDD
Test Points
0.5 EVDD
48
Data Sheet U15203EJ3V0DS
PD77210, 77213
AC Characteristics (TA = - 20 to + 70C, with IVDD and EVDD within recommended operating condition range) Clock Timing requirements
Parameter CLKIN cycle time
Note 1
Symbol tcCX twCXH twCXL trfCX tcC
Condition
MIN. 62.5 12.5 12.5
TYP.
MAX.
Unit ns ns ns
CLKIN high level width CLKIN low level width CLKIN rise/fall time Internal clock cycle time
5 Over 120 MHz(PD77210 only) Under 120 MHz 6.25
ns ns
requirements PLL lock-up time PLL lock frequency Note 1 tLPLL tcPLL
8.33 300
ns
s
MHz MHz
When boot:P3 = 0 Note 2 When boot:P3 = 1
120 80
160 120
Notes 1. The CLKIN cycle time must accord with the PLL lock frequency. It is therefore necessary to satisfy both the CLKIN cycle time condition of 62.5 ns (MIN.) and the PLL lock frequency condition of a multiplied frequency in the range of 80 to 160 MHz. 2. In the PD77213, it can be set only when an external memory boot is being used.
Switching characteristics
Parameter Internal clock cycle
Note
Symbol tcC tcCO twCO n=1 n2
Condition
MIN.
TYP. tcCX / m x n tcC tcC / 2
MAX.
Unit ns ns ns ns ns
CLKOUT cycle time CLKOUT width
High level width Low level width
tcC / n tcC - tcC / n 5 6.25
CLKOUT rise/fall time CLKOUT delay time
trfCO tdCO
ns ns
Note m: Multiple ratio, n: Division ratio (PLL, divider)
Data Sheet U15203EJ3V0DS
49
PD77210, 77213
Clock I/O timing
tcCX twCXH twCXL trfCX trfCX
CLKIN
tcC, tcPLL
Internal clock tdCO twCO tcCO twCO trfCO trfCO
CLKOUT
50
Data Sheet U15203EJ3V0DS
PD77210, 77213
Reset, Interrupt, System Control, Timer Timing requirements
Parameter RESET low level width CSTOP high level width CSTOP recovery time INTmn low level width INTmn recovery time Symbol tw(RL) tw(CSTOPH) trec(CSTOP) tw (INTL) trec (INT) Condition MIN. 6 tcCX
Note 1
TYP.
MAX.
Unit ns ns ns ns ns
12 tcC
Note 2
12 tcC Note 2 6 tcC 6 tcC
Note 3
Note 3
Notes 1. When reset timing, it is specified by input clock. 2. When STOP or HALT mode, it is specified by divided clock. 3. Interrupt can input by TSIEN, TSOEN, ASIEN, and ASOEN pins other than interrupt pins. The interrupt pins function alternately as pins P0 to P15. Remark INTmn m, n = 0 to 3
Switching characteristics
Parameter STOPS output delay time HALTS output delay time TIMOUT output delay time TIMOUT output width Symbol tdSTP tdHLT tdTIM twTIM Condition MIN. 0 0 0 4 tcC TYP. MAX. 6.25 6.25 6.25 Unit ns ns ns ns
Reset timing
tw(RL) RESET
WAKEUP timing
tw(CSTOPH) CSTOP trec(CSTOP)
Interrupt timing
trec(INT) tw(INTL) INTmn
Data Sheet U15203EJ3V0DS
51
PD77210, 77213
Standby mode status output timing
Internal clock
Internal status
Execution STOP or HALT Instruction
Fetch Next Instruction of STOP or HALT
CSTOP tdSTP STOPS
tdHLT HALTS
tdHLT
Remarks 1. Internal clock cycle is changed or stopped to be fixed to low level when STOP or HALT mode. 2. STOPS pin is become low level asynchronously by CSTOP pin rising edge.
Timer time out status output timing
Internal clock
Internal status
Detect Time out
twTIM tdTIM tdTIM
TIMOUT
52
Data Sheet U15203EJ3V0DS
PD77210, 77213
External Data Memory Access Timing requirements
Parameter MD setup time MD hold time MHOLDRQ setup time MHOLDRQ hold time MWAIT setup time MWAIT hold time Symbol tsuMDI thMDI tsuHRQ thHRQ tsuWAIT thWAIT Condition MIN. 17.5 0 11.25 0 11.25 0 TYP. MAX. Unit ns ns ns ns ns ns
Switching characteristics
Parameter MA output delay time MRD output delay time MWR output delay time MD output delay time MBSTB output delay time MHOLDAK output delay time Symbol tdMA tdMRD tdMWR tdMDO tdBS tdHAK Condition MIN. 0 0 0 0 0 0 TYP. MAX. 6.25 6.25 6.25 6.25 6.25 6.25 Unit ns ns ns ns ns ns
Data Sheet U15203EJ3V0DS
53
PD77210, 77213
External data memory access timing (Read)
Internal colck tdMA
tdMA
MA0 to MA19 tsuMDI MD0 to MD15 tdMRD MRD tsuWAIT thWAIT tsuWAIT thWAIT tdMRD thMDI
MWAIT tdBS MBSTB tdBS
Remark In the PD77213, it is possible to shift fall timing of MRD pin by cycle unit, by setting of MSHW register. External data memory access timing (Write)
Internal clock
tdMA
tdMA
MA0 to MA19 tdMDO tdMDO Hi-Z MD0 to MD15 Hi-Z
tdMDO
tdMWR MWR
tdMWR
tsuWAIT
thWAIT
tsuWAIT
thWAIT
MWAIT tdBS
tdBS MBSTB
Remark It is possible to shift rise/fall timing of MWR pin by cycle unit, by setting of MSHW register.
54
Data Sheet U15203EJ3V0DS
PD77210, 77213
Bus arbitration timing
Internal colck
(Bus busy)
Bus busy
Bus idle
Bus release tsuHRQ
Bus idle
(Bus busy) thHRQ
tsuHRQ thHRQ MHOLDRQ tdHAK MHOLDAK tdMA,tdMDO,tdMRD,tdMWR MA0 to MA19, MD0 to MD15, MRD, MWR Hi-Z tdMA,tdMDO,tdMRD,tdMWR tdHAK
Data Sheet U15203EJ3V0DS
55
PD77210, 77213
General-purpose I/O Port Timing requirements
Parameter Port input setup time Port input hold time Symbol tsuPI thPI Condition MIN. 11.25 6.25 TYP. MAX. Unit ns ns
Switching characteristics
Parameter Port output delay time Symbol tdPO Condition MIN. 0 TYP. MAX. 6.25 Unit ns
General-purpose I/O port timing
Internal clock
tdPO P0 to P15 (output) tsuPI thPI P0 to P15 (input)
56
Data Sheet U15203EJ3V0DS
PD77210, 77213
Host Interface Timing requirements
Parameter HRD low level width, recovery time HWR low level width, recovery time HD setup time HD hold time HA, HCS setup time HA,HCS hold time Symbol twHRD Condition MIN. 3 tcC TYP. MAX. Unit ns
twHWR
3 tcC
ns
tsuHDI thHDI tsuHA thHA
6.25 6.25 3 0
ns ns ns ns
Switching characteristics
Parameter HRE output delay time HWE output delay time HD output delay time Symbol tdRE tdWE tdHD Condition MIN. 0 0 0 TYP. MAX. 11.25 11.25 11.25 Unit ns ns ns
Data Sheet U15203EJ3V0DS
57
PD77210, 77213
Host read interface timing
Interanal clock
HCS, HA0, HA1 thHA tsuHA HRD tdHD Hi-Z tdRE tdHD Hi-Z twHRD twHRD
HD0 to HD15
tdRE
HRE
Host write interface timing
Internal clock
HCS, HA0, HA1 thHA tsuHA HWR thHDI tsuHDI HD0 to HD15 tdWE twHWR twHWR
tdWE
HWE
58
Data Sheet U15203EJ3V0DS
PD77210, 77213
Serial Interface (Standard Serial mode/ TDM serial mode) Timing requirements
Parameter ASCK cycle time Symbol tcSC Condition MIN. 50 and 2 tcC 25 20 12.5 12.5 TYP. MAX. Unit ns
ASCK high /low level width ASCK rise/fall time Serial input setup time Serial input hold time
twSC trfSC tsuSER thSER
ns ns ns ns
Switching characteristics
Parameter Serial output delay time Symbol tdSER Condition MIN. 0 TYP. MAX. 17.5 Unit ns
Data Sheet U15203EJ3V0DS
59
PD77210, 77213
Serial output timing 1
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSORQ tsuSER tsuSER thSER ASOEN, TSOEN tdSER ASO, TSO Hi-Z tdSER thSER Last thSER
1st
Note When TDM mode, TSO output value is delay for a bit according to TDM setting value.
Serial output timing 2 (during successive output)
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSORQ tsuSER thSER ASOEN, TSOEN tdSER ASO, TSO thSER 1st Last Hi-Z
Last
Note When TDM mode, TSO output value is delay for a bit or dummy cycle (high impedance) is inserted,
according to TDM setting value.
60
Data Sheet U15203EJ3V0DS
PD77210, 77213
Serial input timing 1
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSIAK tsuSER tsuSER thSER ASIEN, TSIEN tsuSER ASI, TSI 1st thSER 2nd 3rd thSER
Note When TDM mode, TSI input value is delay for a bit according to TDM setting value.
Serial input timing 2 (during successive input)
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSIAK tsuSER thSER ASIEN, TSIEN
tsuSER
ASI, TSI
thSER
Last-1
Last
1st
2nd
3rd
Note When TDM mode, TSI input value is delay for a bit or skip cycle is input, according to TDM setting value.
Data Sheet U15203EJ3V0DS
61
PD77210, 77213
Serial Interface (Audio Serial mode) Timing requirements
Parameter MCLK cycle time Symbol tcMC Condition Master mode MIN. 50 and 2 tcC 25 20 50 and 8 tcC 25 20 12.5 25.0 12.5 25.0 TYP. MAX. Unit ns
MCLK high/low level width MCLK rise/fall time BCLK cycle time
twMC trfMC tcBC
Master mode Master mode Slave mode
ns ns ns
BCLK high/low level width BCLK rise/fall time Serial input setup time
twBC trfBC tsuASER
Slave mode Slave mode Slave mode Master mode
ns ns ns ns ns ns
Serial input hold time
thASER
Slave mode Master mode
Switching characteristics
Parameter BCLK cycle time Symbol tcBC Condition Master mode MIN. 50 and 8 tcC 25 5 -12.5 0 +25.0 17.5 TYP. MAX. Unit ns
BCLK high/low level width BCLK rise/fall time Serial output delay time
twBC trfBC tdASER
Master mode Master mode Master mode Slave mode
ns ns ns ns
62
Data Sheet U15203EJ3V0DS
PD77210, 77213
Audio serial clock timing
tcMC twMC twMC trfMC trfMC
MCLK
Audio serial master mode timing
tcBC twBC BCLK (output) tdASER LRCLK (output) tdASER ASO tsuASER thASER tdASER twBC trfBC trfBC
ASI
Audio serial slave mode timing
tcBC twBC BCLK (input) tsuASER LRCLK (input) tdASER ASO tsuASER thASER tsuASER twBC trfBC trfBC
ASI
Data Sheet U15203EJ3V0DS
63
PD77210, 77213
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in mind the following points when designing your system: * Reinforce the wiring for power supply and ground (if noise is superimposed on the power and ground lines, it has the same effect as if noise were superimposed on the serial clock). * Shorten the wiring between the device's ASCK, TSCK, BCLK pins, and clock supply source. * Do not cross the signal lines of the serial clock with any other signal lines. Do not route the serial clock line in the vicinity of a line through which a high alternating current flows. * Supply the clock to the ASCK, TSCK, BCLK pins of the device from the clock source on a oneto-one basis. Do not supply clock to several devices from one clock source. * Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure that the rising and falling of the serial clock waveform are clear.
x Make sure that the serial clock rises and falls linearly. The serial clock must not bound. Noise must not be superimposed on the serial clock.
x The serial clock must not rise or fall step-wise.
64
Data Sheet U15203EJ3V0DS
PD77210, 77213
SD card Interface (PD77213 only) Timing requirements
Parameter SDCR input setup time SDCR input hold time SDDAT input setup time SDDAT input hold time Symbol tsuSDCR thSDCR tsuSDD thSDD Condition Input response Input response Input data Input data MIN. 10 0 10 0 TYP. MAX. Unit ns ns ns ns
Switching characteristics
Parameter SDCLK cycle time SDCLK high level width SDCLK low level width Symbol tcSDC twSDC(H) twSDC(L) Condition MIN. TYP. n x tcC
Note
MAX.
Unit ns ns ns
2 tcC tcSDC - twSDC(H) 5 Output command Output command Output data Output data 0 0 10 10
SDCLK rise/fall time SDCR output delay time SDCR output valid time SDDAT output delay time SDDAT output valid time
trfSDC tdSDCR tvSDCR tdSDD tvSDD
ns ns ns ns ns
Note n:SD card clock division ratio
Data Sheet U15203EJ3V0DS
65
PD77210, 77213
SDCR timing
tcSDC twSDC(L) twSDC(H) trfSDC trfSDC
SDCLK
tdSDCR SDCR (Output) tsuSDCR thSDCR SDCR (Input)
tvSDCR
SDDAT timing
tcSDC twSDC(L) twSDC(H) trfSDC trfSDC
SDCLK
tdSDD SDDAT0 (Output) tsuSDD thSDD SDDAT0 (Input)
tvSDD
Remark The SDMON pin functions alternately as the external data memory interface pin MA13. When accessing a peripheral register related to the SD card interface, the SDMON (MA13) pin becomes high level, and the MA0 to MA12 pins become low level. For the timing of these pins, refer to External Data Memory Access.
66
Data Sheet U15203EJ3V0DS
PD77210, 77213
Debugging Interface (JTAG) Timing requirements
Parameter TCK cycle time Symbol tcTCK Condition MIN. 50 and Note 2 tcC 25 20 12.5 12.5 12.5 12.5 100 TYP. MAX. Unit ns
TCK high/low level width TCK rise/fall time TDI input setup time TDI input hold time Input pin setup time Input pin hold time TRST low level width
twTCK trfTCK tsuTDI thTDI tsuJIN thJIN twTRST
ns ns ns ns ns ns ns
Note When using debugger, the value is 50 and 2 tcCX (MIN.).
Switching characteristics
Parameter TDO output delay time Output pin output delay time Symbol tdTDO tdJOUT Condition MIN. 0 TYP. MAX. 17.5 17.5 Unit ns ns
Data Sheet U15203EJ3V0DS
67
PD77210, 77213
Debugging interface timing
tcTCK twTCK twTCK trfTCK trfTCK
TCK
twTRST
TRST tsuTDI thTDI
TMS, TDI
Valid
Valid
Valid
tdTDO
TDO
tsuJIN thJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
68
Data Sheet U15203EJ3V0DS
PD77210, 77213
11. PACKAGE DRAWINGS
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A B
108 109 73 72
detail of lead end
S C D R Q
144 1
37 36
F G P
H
I
M
J
K
S
N
S
L M
NOTE
Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.08 1.40.05 0.100.05 +4 3 -3 1.6 MAX. S144GJ-50-8EN-1
Data Sheet U15203EJ3V0DS
69
PD77210, 77213
161-PIN PLASTIC FBGA (10x10)
ZD E w SB ZE B
A D
14 13 12 11 10 9 8 7 6 5 4 3 2 1 P NML K J HG F EDC B A
INDEX MARK
w
SA
A y1 S A2 S
y
S
e
A1
b
x
M
SAB
ITEM D E w A A1 A2 e b x y y1 ZD ZE
MILLIMETERS 10.000.10 10.000.10 0.20 1.230.10 0.300.05 0.93 0.65 0.400.05 0.08 0.10 0.20 0.775 0.775 P161F1-65-DA2
70
Data Sheet U15203EJ3V0DS
PD77210, 77213
12. RECOMMENDED SOLDERING CONDITIONS
The PD77210 Family should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Surface Mounting Type Soldering Conditions
PD77210F1-DA2:161-pin plastic fine pitch BGA (10 x 10) : PD77213F1-xxx-DA2:161-pin plastic fine pitch BGA (10 x 10) :
Soldering method Soldering conditions Recommended condition symbol IR35-107-2
Infrared reflow
Package peak temperature: 235 C, Time: 30 sec. Max. (at 210 C or higher). Count: two times or less Exposure limit: 7 days Note (after that prebaking is necessary at 125 C for 10 to 72 hours)
PD77210GJ-8EN:144-pin plastic LQFP (fine pitch) (20 x 20) : PD77213GJ-xxx-8EN:144-pin plastic LQFP (fine pitch) (20 x 20) :
Soldering method Soldering conditions Recommended condition symbol IR35-103-2
Infrared reflow
Package peak temperature: 235 C, Time: 30 sec. Max. (at 210 C or higher). Count: two times or less Exposure limit: 3 days Note (after that prebaking is necessary at 125 C for 10 to 72 hours) Pin temperature: 300 C Max. , Time: 3 sec. Max. (per pin row)
Partial heating
-
Note After opening the dry pack, store it at 25 C or less and 65 % RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for the partial heating).
Data Sheet U15203EJ3V0DS
71
PD77210, 77213
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
72
Data Sheet U15203EJ3V0DS
PD77210, 77213
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet U15203EJ3V0DS
73
PD77210,77213
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed:
PD77210F1-DA2, PD77210GJ-8EN
The customer must judge the PD77213F1-xxx-DA2, PD77213GJ-xxx-8EN
* The information in this document is current as of November, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

▲Up To Search▲

Price & Availability of UPD77210F1-DA2

	To Download UPD77210F1-DA2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .